1. Filed of the Invention
The present invention relates to a pipelined computer, and more specifically, to a control of a program counter used in a pipelined computer.
2. Description of Related Art
In advanced computers, the architecture has been improved in various points so as to comply with high level languages and a common operation system. Particularly, a relocatable program has been widely used, since standard programs can be placed at any location in an address space. It is very advantageous in such an environment that the same program is used in a plurality of situations.
As a means for easily realizing the relocatable program, there is provided a so-called program counter/relative addressing mode, which can minimize the modification of a code required to relocate the program. Various central processing units which realize the program counter/relative addressing mode have been already used. As regards the details, reference should be made to, for example, "VAX Architecture Handbook", Digital Equipment Corporation; "MC 68020 User's Manual", Motorola, Inc.; "Z80000 CPU Technical Manual", Zilog; and "NS 32032 Instruction Set Reference Manual", National Semiconductor Corp.
In most of the conventional central processing units having the program counter/relative addressing mode, the architecture adopts a hardware structure processing the instruction decoding and the operand address calculation without distinguishing them from each other. Therefore, it has been ordinary that the value of a program counter at the time of address calculation indicates a head or a tail of one portion of a given instruction which includes the information relating to the address calculation. For example, reference can be made to the program counter/relative addressing mode adopted in the VAX-11 machine of Digital Equipment Corporation. The above referred "VAX Architecture Handbook" shows on page 110 one example of an instruction "MOVE LONG WORD" in the VAX-11 machine. This example is shown in FIG. 3. The address of the first operand is not an instruction head address "00001012.sub.h " (the surfix "h" means a hexadecimal notation), but is "00002016.sub.h " obtained by adding the displacement "1000.sub.h " to the address "00001016" of the tail of a portion including the information concerning the address of the first operand.
In the prior art, in the case of modifying the hardware architecture of the central processing unit so as to improve its performance while maintaining compatibility at the object code level, it has been necessary to quickly obtain the value of the program counter required in calculation of the program counter/relative address, i.e., an intermediate result of the program counter modified in accordance with the progress of the instruction decoding operation. However, an instruction set having a high level function and a plurality of instructions has been heretofore expressed in the form of a variable word length instruction. In addition, the length of the instruction is greatly dependent upon the content of the instruction itself. For example, the length of the instruction is dependent upon:
(11) the number of operands designated by the instruction (0th operand, 1st operand, 2nd operand, . . . );
(2) the addressing information of the operand (additional information such as index modification, displacement, immediate data, etc.);
(3) the encoding of the instruction operand (instructions having a high use frequency are encoded as short as possible).
Japanese Patent Publication No. Sho 59-31733 (Convention Priority: U.S. patent application Ser. No. 854,055 filed Oct. 25, 1977, abandoned, continuation-in-part Ser. No. 954,453, now U.S. Pat. No. 4,236,206 discloses one example of the program counter/relative address calculation in the above mentioned manner of VAX-11. In this example, not only the displacement "1000.sub.h " but also one byte defining the operation of an instruction, another byte indicating that the first operand is the program counter/relative addressing, and two bytes showing the displacement for the address calculation of the first operand must be added to the head address "00001012.sub.h " of the instruction.
As seen from the above, the fact that the result of the instruction decoding operation is used in the operand address calculation, means that the two kinds operation have a high mutual dependence. In other words, the two kinds of operation have only a small independence from each other. This is one hinderance in increasing a parallel processibility of the two kinds of operations. This inclination is enhanced if there is added a high level function program counter/relative addressing mode such as index.
From a different viewpoint, the increase of the elements to be added for the address calculation is disadvantageous to the variable word length instruction. Particularly, the address calculation of 32 bits or more is inconvenient to a carry transfer control. Specifically, one or more times of calculation are required at the time of the address calculation in order to amend the program counter indicating the head of the current instruction. In this case, a carry must be transferred over a long bit length of 32 bits or more. Therefore, the timing of control is limited since it must wait for the transfer of the carry. In order to overcome this problem, a "carry lookahead" method or a "carry reservation" method can be used for the speed-up the operation. But, an additional hardware resource is necessary for executing such a method, and so, it is expensive.